A field programmable gate array is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a field programmable gate array, the user configures an on-chip interconnect structure of the field programmable gate array so that selected inputs and selected outputs of selected on-chip logic components are connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. For additional background on antifuse-based field programmable gate array structures, the reader is referred to: U.S. Pat. Nos. 5,495,181, 5,424,655, 5,122,685, 5,055,718, 4,873,459, 5,502,315, 5,362,676, 5,557,136, 5,308,795 and 5,233,217; U.S. patent application Ser. No. 08/667,702 now U.S. Pat. No. 5,825,201 issued on Oct. 10, 1998 entitled "ramming Architecture For A Programmable Integrated Circuit Employing Antifuses" by Paige A. Kolze, filed Jun. 21, 1996; the 1996/97 QuickLogic Data Book; the 1996 Actel FPGA Data Book and Design Guide; and the book entitled "Field-Programmable Gate Arrays" by Stephen Brown et al., Kluwer Academic Publishers (1992) (the subject matter of these documents is incorporated herein by reference).
FIG. 1 (Prior Art) is a top-down diagram of a first conventional field programmable gate array 1 (for example, the QL 16X24 QuickLogic field programmable gate array in the pASIC1 family). Field programmable gate array (FPGA) 1 includes a plurality of interface cells 2, a plurality of logic modules 3 arranged in rows and columns, and a programmable interconnect structure 4 employing antifuses. The programmable interconnect is disposed in spaces between the rows and columns of logic modules.
FIG. 2 (Prior Art) is a top-down diagram of a matrix of locations. Many of the antifuses of the programmable interconnect structure of FPGA 1 are disposed in such a matrix. The rows of locations are labeled with row designators RA, RB, RC and so forth. The columns of locations are labeled with column designators C1, C2, C3 and so forth. For each column, there is a vertically extending column conductor (not shown) that extends underneath the locations of its column. For each row, there is a horizontally extending row conductor (not shown) that extends underneath the locations of its row. The row conductors extend in a plane over the plane of the column conductors. Antifuses are disposed at the locations illustrated in FIG. 2 where the row conductors cross the column conductors. For example, to couple vertically extending column conductor C3 to horizontally extending row conductor R4, an antifuse disposed at location C3/R4 would be programmed. The lateral distance DIS between respective antifuses in a row and between respective antifuses in a column is the minimum lateral spacing between antifuses on the FPGA. No two antifuses of the FPGA are separated by a lateral distance smaller than lateral distance DIS. In FPGA 1, some of the matrix locations are not populated with antifuses. Some of the conductors are made wider to reduce conductor resistance to speed the propagation of signals through the conductor. Distances greater than distance DIS separate some of the rows and/or columns to accommodate wider conductors.
In this first conventional FPGA: 1) the antifuses are conductive plug-type antifuses (for more details on conductive plug-type antifuses, see the description below); 2) none of the antifuses has an associated programmable material corner under a metal conductor within lateral distance DIS of the conductive plug of the antifuse (for more details on what such a programmable material corner is, see the description below); and 3) approximately 20 percent of the antifuses have programmable material edges under a metal conductor within lateral distance DIS of the conductive plug of the antifuse (for more details on what such a programmable material edge is, see the description below).
FIG. 3 (Prior Art) is a top-down diagram of two antifuses 5 and 6 of a second conventional FPGA (for example, the QL2007 QuickLogic FPGA in the pASIC2 family). To increase packing density in this second conventional FPGA, the spaces between logic modules of the first conventional FPGA are substantially eliminated in the center portion of the integrated circuit and the programmable interconnect structure is disposed in layers above the logic modules. A matrix of antifuses is disposed over each respective logic module. For example, an antifuse 5 is disposed at location RB/C1 and an antifuse 6 is disposed at location RB/C3. There is no antifuse at location RB/C2. An inter-metal layer insulator covers the underlying column conductors and separates the column conductors from the overlaying row conductor. If programmed, antifuse 5 would couple vertically extending column conductor 7 to overlaying horizontally extending row conductor 8. If programmed, antifuse 6 would couple vertically extending column conductor 9 to horizontally extending row conductor 8.
In the second conventional FPGA, the antifuses are also conductive plug-type antifuses. Each conductive plug-type antifuse includes a conductive plug and a layer of a programmable material disposed over the conductive plug between the top of the plug and the bottom of the overlaying row conductor. The conductive plug is disposed in an opening in the inter-metal layer insulator. When programmed, a conductive filament forms through the layer of programmable material to couple the conductive plug to the overlaying row conductor. For additional background information on conductive plug-type antifuse structures and how to make them, see U.S. Pat. Nos. 5,557,136, 5,308,795 and 5,233,217, and the U.S. patent application No. 09/133,998, now allowed entitled "Metal-to-Metal Antifuse Having Improved Barrier Layer", by Rajiv Jain et al., filed Aug. 13, 1998 (the subject matter of these patents and this patent application is incorporated herein by reference).
FIG. 4 (Prior Art) is a cross-sectional diagram taken along sectional line SS' of FIG. 3. Layer 10 is a layer of insulation (for example, silicon dioxide). The antifuses are disposed in layers above the substrate such that layer 10 insulates the antifuse and programmable interconnect layers from underlying logic module transistors in the substrate. Column conductor 7 and column conductor 9 each includes a bottom barrier layer (for example, TiW or TiN), a relatively thick layer involving aluminum, and a top barrier layer (for example, TiW or TiN). Conductive plugs 5P and 6P of antifuses 5 and 6 are disposed in openings in inter-metal layer insulation 11. The center axis 5PA of conductive plug 5P is located at location RB/C I and the center axis 6PA of conductive plug 6P is located at location RB/C3. Each conductive plug involves a thin binding layer of titanium and/or TiW or TiN as well as the bulk plug material, which in this case is tungsten. Overlaying the conductive plugs is a layer of the programmable material 12. The layer of programmable material is intrinsic plasma enhance chemical vapor deposited (PECVD) amorphous silicon and is disposed substantially in a plane 12A. Row conductor 8, like column conductors 7 and 9, includes a bottom barrier layer (for example, TiW or TiN), an intervening aluminum layer, and a top barrier layer (for example, TiW or TiN).
The bottom barrier layer of row conductor 8 prevents aluminum from row conductor 8 from migrating into the programmable material 12 and adversely affecting antifuse characteristics. A "programmable material plug overlay design rule" used in generating the layout of the second conventional FPGA ensures that the programmable material covers the top of the conductive plugs and extends in a lateral dimension past the top edges of the conductive plugs by at least a lateral distance 13. Because there is no antifuse disposed at location RB/C2, use of the design rule results in two edges 14 and 15 of the programmable material 12 located at distance 13 from the conductive plugs 5P and 6P, respectively.
FIG. 5 (Prior Art) is a top-down diagram of another antifuse structure in the second conventional FPGA where the programmable interconnect is disposed over the logic modules. Here row conductor 8 is made wider to reduce resistance and to decrease the propagation time of signals down the row conductor. Not only are edges 14 and 15 of the programmable material disposed underneath row conductor 8, but corners 16-19 of the programmable material are now also disposed underneath row conductor 8. In addition to the configurations of FIGS. 3 and 5, there are other antifuse structures of the second conventional FPGA that result in programmable material edges and corners being disposed underneath overlaying metal conductors.
In this second conventional FPGA: 1) approximately 4% of the antifuses have an associated programmable material corner under a metal conductor within lateral distance DIS of the conductive plug; and 2) approximately 90% of the antifuses have an associated programmable material edge under a metal conductor within lateral distance DIS of the conductive plug. Reducing such edges and corners is desired to increase yield and to improve reliability of an FPGA such as the second conventional FPGA where conductive plug-type antifuses are disposed in a layer (or layers) above logic modules.